Research And Implementation Of Test Pattern Compression Based On Golomb Code

With the rapid development of semiconductor technology and integrated circuit fabrication technology , the appearance of system chip SoC (system on chip) becomes the mainstream of and occupy the development stage a large scale integrated circuit .Many composite modules are integrated on a single chip, and will be able to accomplish more complex tasks. On the other hand, because the market increase urgently for the demand of the chip design cycle, so that the model of SoC chip massively adopted pre-designed and integrated IP (intellectual property) module to reduce production time. But following gives rise to the question, because its scale is huge so that chip manufacturing fault increased subsequently.Therefore,the test chip put forward higher request. Not only need to be more precise control sequence, but also need longer microchip testing time, these will lead to increase the cost of test. Test data compression is a method that it can solve such problems of SoC testing cost, it can reduce the required test storage test data quantity, reduce test time. In order to test the convenience and integrity, each IP core producers in the supply of IP core will also additional supply the chip test vectors. In general average SoC chip has tens of billions of bit of test vectors. Testing data quantity can reduce to above 20 times after testing the vector compression.On the basis of depth study about various testing compression technology, this thesis focus on researching several methods which encoding compression test vector method.Comparing with them from compression ratio and decoder circuit scale angle, it is concluded that Golomb is a simple and effective method that can code to test vector compression. The biggest characteristic of Golomb code is to choose the length to variable-length coding method, which can reduce code word length of growth rate. At the same time, aiming at the characteristics of Golomb coding run-length coding length disperse and not free compressed, propose a method that based on group frequency Golomb code compression method, and use ISCAS85 benchmark recognized in the circuit C17 logic circuit for circuit under test conducted experiments that converts coded after testing vector input to design good decoder circuit of, then they can release the original test vectors by the decoder.Finally, circuit finish all the test by exert test vector on C17.This scheme experiment on benchmark cicuit, from the simulation of the actual test results look, the software and hardware design of test system achieved the design goal, and each index all conform to the requirements of SoC test. In a small increase in the amount of unzip circuit under test vector compression price have a better compression ratio, which reduces the test cost. We could achieve practical level as long as we improve them.