Hierarchical Symbolic Sensitivity Analysis With Application To Analog Design Optimization

In this thesis, a method of hierarchical symbolic sensitivity analysis is proposed, including sensitivity of common circuit device and MOSFETs. Due to the good structure of BDD and a carefully designed algorithm, the sensitivity calculation process is easy to implement. The sensitivity analysis method we proposed can help analog designers for circuit design optimization.The thesis is divided into six chapters. The concept of symbolic analysis and sensitivity are first introduced in chapter 1 and then two most successful symbolic simulators, GRASS and DDD, along with a hierarchical simulator based on a combination of the two, are briefly described in chapter 2. In Chapter 3, we designed the computation process of device sensitivity, including common linear device or MOSFETs. Chapter 4 and chapter 5 show the experimental results of the sensitivity theory and comparison with differential method by HSPICE. Chapter 6 summarized the above chapters. The hierarchical sensitivity calculation method we proposed is capable of analyzing very large scale analog circuit, with good efficiency and it's a good trial toward automated analog design.