Low Power SRAM Research And Design Under Near-Threshold Voltage Supply

The research work of memory has always been a hot topic in the region of semiconductor trade. While in the family of the semiconductor memory, the Static Random Access Memory (SRAM) plays a very important role. Considered about the hot point of low-power, high-performance research, the paper designed SRAM architecture under the theory of Near-Threshold Computing (NTC).The paper firstly illustrated the general architecture of SRAM circuit, including the memory cell and periphery circuit. By using the traditional 6T SRAM as an example, introduced the operating principle of the circuit. After analyzed the shortcomings of traditional circuit under the low voltage supply, including the large variation of circuit output and functional failure caused by enlarged delay, the paper designed 7T SRAM architecture by departing the function line between read and write to fit the situation. The parameters, including threshold voltage and unit size of the transistors, in 7T SRAM circuit are also designed, so as to ensure robustness and improve performance of the circuit. Then, a HSPICE simulation was made to ensure the logic of the circuit is still available under near-threshold voltage supply. It is demonstrated that the average power dissipation of the SRAM cell is 72.55μW, and the maximum circuit delay for writing operation is 40ns, yet 35ns for reading operation. At the end, the periphery circuit, including address decoding circuit and amplifier circuit, are also designed under near-threshold voltage. By HSPICE simulation, the circuits are demonstrated to be rational under near-threshold voltage, and do have the feature of low-power and high-performance.