C*CORE Processor Modeling Based On ESL

With the system on a chip (SoC) development, a growing number of embedded microprocessors and peripherals are integrated into one chip, and the complexity of SoC design is showing exponential growth. SoC hardware and software integration and optimization of more complex system architecture development have led to a sharp increase in the workload, and to extend the SoC system development cycle, including software development, hardware development and system verification time. The increasing demand of low power consumption and reducing time to market forces the lower level of abstraction at the RTL for SoC design development not meet the requirements of simulation time. New electronic system level (ESL) design methodology overcomes the challenges faced by the RTL design. ESL design in an abstract way to describe the SoC system provides hardware and software engineers with a virtual hardware prototyping platform for early system architecture exploration and software application development. ESL design can provide a faster simulation speed than RTL and the different levels of abstraction timing accuracy according to actual needs, for the assessment of overall system performance SoC.Using emerging ESL design methodology, this paper designs C*CORE embedded microprocessor hybrid model, including the ISS and Cache, and describes the implementation process of ISS and Cache based on ESL design methodology in detail. Furthermore, it introduces the method of integration the C*CORE hybrid model into French SoCLib platform. Finally, functional testing and performance evaluation are done in SoCLib for C* CORE hybrid model. Experiments show that compared with RTL model, the hybrid model has a great advantage in simulation speed, and ensures the simulation accuracy.