Research On Hop-by-hop Fault Tolerant Mechanism For Soft Error And Task Mapping For Reliability In NOC

With the development of integrated circuits technology, more and more resources are available on chip. Multi-core architecture design has become the main trend. However, the shrinking geometry makes the wire delay more than the gate delay. So the communication among the cores becomes a bottleneck to improve the performance. Network on Chip was introduced to replace the traditional bus for its high bandwidth and low latency, and is the most promising method.Scaling also affects the reliability of the circuit. It's more sensitive to the impact of yield and interference outside. Soft errors and hard errors happen more. Particularly, the soft errors change the contents in the routers and links, but don't change the physical circuits. It's unable to predict the soft error during manufacturing, but may make the system break down during running. So it's important to have fault tolerant mechanism in the system.In this paper, four hop-by-hop fault tolerant mechanisms were designed, implemented and tested. They are based on extended Hamming Code and Cycle Redundancy Code, and designed to tolerant the soft errors happens in the links. The performance of the fault tolerant method is measured in a cycle accurate system simulator. The result of the performance of all the fault tolerant mechanisms should be a good reference for the NoC designers.As the mapping algorithm is an important issue for the NoC design, I take the fault-tolerant mechanism into consideration and make a completed communication cost function modeling. Finally, I proposed an improved mapping algorithm based on the greedy method to improve the reliability in a high level. With the simulation result, it's verified to be effective.