Designing And Implementation Of AHB Bus In Multimedia SoC

SoC on a single chip implement a complete system function.How to expedite the SoC of the each IP core information interaction, easier to more convenient integrated IP core, establish more correct and efficient, flexible chip bus structure, becoming a very important SoC design topic.Taking reconfigurable multimedia SoC project design as the background, using TSMC 65nm process, the design realized AHB bus architecture and given a thorough analysis and simulation. The main contents and highlights of this paper are as follows:1. According to the design of multimedia SoC chip goals and application requirements. From interconnection method, transmission, arbitration mechanism and bus complexity, analysis of several popular buses on chip bus, using AMBA bus as the multimedia SoC chip internal interconnection architecture.2. Complete the logic of AHB bus design and optimization.The design supports single and ambiguity length and 4,8,16 and 32 pat fixed length burst transmission. Supports EMI HSPLIT transmission, supports LCDC, ARM and DMA lock transmission and 32-bit data bus bandwidth.3. Analysis multimedia SoC AHB bus arbitration basic algorithm: fixed priority algorithm and circulation priority algorithm, and combining multimedia SoC project requirements and masters (LCDC AHB bus, ARM, REmus, SD and the DMA) data transmission characteristics and occupy bus bandwidth, the design based on mixed priority algorithm AHB bus architecture of arbitration algorithm.4. Complete system-level multimedia SoC AHB bus simulation.Based on the ARM validation platform through constructing hierarchic verification environment, define test strategy, efficiently realized LCDC, ARM and DMA masters module interaction.5. Complete multimedia SoC AHB bus logic synthesis and timing optimizing,with optimization strategies on the structural level and code level.Design realized the high-speed bus design requirement with a 200MHz on the multimedia SoC chip.