Study Of Satellite-Ground High Speed Data Transmission Demodulation Technique

The quality of remote sensing information will be improved and the real-time data transmission rate will reach Gbps along with development of the high-resolution remote sensing satellite in our country. At present, the satellite-ground high speed data transmission technique of our country is able to transmit information with several hundreds of Mbps data rate. Because Mbps code rate can not satisfy the requirement of high speed data transmission, it is necessary to develop the high speed data transmission technique with Gbps data rate.This paper starts with the characteristic of satellite-ground high speed data transmission system and the high speed data demodulation technique is studied. The scheme of high speed data demodulation which includes hardware platform design and the high speed data demodulation algorithm is firstly proposed, and then the project design is verified by computer simulation. The researches of this paper are as follows:1.The scheme of high speed demodulation is firstly selected, and then transmission mode of high speed data transmission system and system parameters are analyzed. By comparing three kinds of high speed demodulation methods, A zero-IF demodulation scheme with Gbps data rate is selected and the system parameters are confirmed.2.High speed data demodulation hardware platform with Gbps data rate is realized. Every part of the platform including analog front end (filter, AGC, I/O demodulator, carrier recovery, timing recovery), high speed analog to digital conversion circuit and digital signal processing circuit is analyzed and the technical index is confirmed. A 4Gbps analog to digital conversion circuit is realized by using double AD sampling scheme. A high speed PCB design method and attentions is proposed by considering signal integrality and power integrality.3.A high speed digital demodulation algorithm is presented and a parallel demodulation structure is introduced in the design. Digital processing demodulation algorithm which supports Gbps data rate is realized by designing high speed parallel digital matching filter, AGC, high speed parallel carrier recovery, high speed parallel timing recovery and high speed adaptive equalization and the FPGA source cost is presented.4.The performance of this high speed digital demodulator is tested. The testing method of input signal dynamic range and bit error rate is proposed in the paper. The experimental result is that when the bit error rate is 1×10-7, the demodulation loss is 2.1dB which indicates that the design of this high speed digital demodulator is satisfying.