Optimization And Realization For Sparse Matrix-Vector Multiplication On FPGA

Sparse Matrix-Vector Multiplication is a computation kernel in many engineering and scientific computation. With the extensive use of FPGA, some in-depth research have been done on SMVM based FPGA. By using the parallelism of FPGA, some researchers have designed some computation architecture of SMVM by hardware logic and achieved good computational performance. But there are few shortcomings on these computation architecture, shortcomings are about low utilization of chip resources and poor flexibility. In this paper, the typical architecture based hardware logic has been optimized by using the idea of hardware and software co-design. At last the computing architecture based multi-core added with co-processing unit has been designed and used it to implement SMVM computing system.First, the background and profile of research on SMVM are introduced. And then this paper introduces the basic concepts involved in SMVM. Through introducing FSL bus extension of the Microblaze soft core processor, this paper introduces a method of realizing hardware acceleration and multi-core by FSL bus. The binary tree computing architecture which contains four multipliers has been optimized through analyzing on the binary tree computing architecture which is realized by hardware logic. And then the computing architecture based multi-core added with co-processing unit is given. During the optimization process, the decomposition method is used. And this paper also introduces one method of multiple processors controlling the co-processing unit. Hardware can be called by software by using this method. At last, SMVM computing system is realized by using computing architecture based multi-core added with co-processing unit, and this paper also gives some results about this SMVM computing system through simulation analysis...