Fabrication Technology And Characteristic Research Of SOI Power Devices With A Gradient Surface In Drift Region

VLT is a novel technology which can greatly improve the breakdown voltage and reduce specific on-resistance. However, the biggest challenge is how to manufacture the gradient drift region thickness increasing from the source to the drain. In this thesis, the issue is addressed and investigated in detail.First, a new method to fabricate the gradient silicon surface based on multi-window reactive ion etching technology is proposed. Single window and multi-window etching profile model are developed. The numerical algorithm is deceived to optimize the width, spacing and number of the window. A MATLAB program is designed based on the algorithm. The results computed by this program are substituted into Silvaco TCAD tools for performing the process simulation. An ideal smooth gradient surface is obtained at last.Secondly, this paper puts forward a gradient surface preparation method based on multi-window wet etching technology. Single window and multi-window etching profile model are set up, numerical algorithms are determined which is used to optimize the width, spacing and the number of window, and the MATLAB program is recompiled. Then the results calculated from this program are substituted into Silvaco TCAD tools for process simulation, a smooth surface ideal tilted surface is obtained at last as well.Thirdly, the process design and optimization are implemented for the VLT SOI LDMOS. A CMOS-compatible technology is proposed to manufacture the VLT SOI LDMOS. The process conditions and parameters are optimized by using Silvaco TCAD. The results show that the proposed process can form any shape of the gradient surface just through one additional mask, which provides a new way with lower cost, higher efficiency, and better effect for fabricating the VLT SOI LDMOS.Finally, we research the operating characteristics of the VLT SOI LDMOS. An analytical model of specific on-resistance is developed. The on-resistance, breakdown voltage and the output characteristics of the device are studied using Silvaco TCAD. At last, a high performance VLT SOI LDMOS with the breakdown voltage of 345V, and on-resistance of 1.95?/mm2 is designed.