High-performance, Low-power Multi-port Register File With Full Custom Implementations

Register Files are essential building blocks in high-performance superscalar embedded micro-processors. High performance requires the register files have short access latency, while embedded application focuses on running power and standby power. Superscalar CPUs need the register files have multiple read and write ports. Therefore, design a register file that owns features of high-performance, low-power and multi-ports is exactly a meaningful work. In this thesis, the full-custom design methodology has been adapted to implement a 4R/2W 32x32b register file in 65nm CMOS LP technology.The main contribution can be concluded as followings:(1) Generally, register files are usually implemented by way of SRAM with multiple ports. Firstly, the organization and the working theory of the SRAM are briefly reviewed. The main techniques in the design of the address decoder, memory cell, read and write path circuits and timing control scheme are introduced. The advantages and disadvantages between different techniques have been discussed.(2) This thesis proposes a register file architecture based on sense amplifier technique and double ended read/write memory cell.The address decoder uses two stage static decoders for low power and high performance. The memory array consists of double ended read/write memory cell. Voltage sense amplifier is added in the read path to reduce the access latency and power. The inverter chain timing control scheme is used to insure correctly read and write operation in a single clock phase. The post layout simulation indicates the proposed register file can operate at 1.56GHz (TT corner,1.2V supply,50℃) and consume less than 36mw total power at 1.25GHz clock rate.The core size is 0.043mm2.(3) Another register file based on bit line divided technique and single ended read access memory cell is described in this thesis. Some low power techniques are adapted such as split bit line technique, two stage static decoder, single ended read access memory cell, clock gating and split decoder for low power. The post layout simulation indicates this version can operate at 1 GHz and consume 24mw total power with the core area 0.046mm2.(4) This thesis proposes another register file architecture based on bit line divided technique and dynamic single ended read access memory cell. Since the single ended read memory cell is adapted, the area of memory array is dramatically reduced。The total area of the register file is reduced to 0.01 mm2. At the same time, due to the reduction of area, the performance is improved to 2.2GHz in conventional PVT environment and power dissipation is reduced to 11.4mw at 1GHz clock rate.