Wireless Communication Transmitter System And Key Module For Wcdma And Quad-band Gsm Protocol

With the prosperous and high-speed development of the wireless communication, cellphone is playing a more and more indispensable role in our daily life. Represented by Wideband Code Division Multiple Access (WCDMA), the 3rd Generation Wireless Communication System is widely adopted in developed country nowadays. Although the GSM-based 2nd Generation Communication System still holds its dominant place in the developing countries, more and more are stepping into the transition from 2nd to 3rd generation system. Hence there is a large market for the multi-mode transceiver that is compatible with both GSM and WCDMA. The dissertation mainly focuses on the design of a multi-mode wireless transmitter used for WCDMA and GSM.The dissertation starts from analyzing the GSM protocol and 3GPP protocol, according to which the system level specification is defined. Considering the application environment of the chip especially the selection of the off-chip component (Power amplifier, SAW, Duplexer, Switch), the system architecture is carefully designed and the specification for each module is achieved with calculation together with simulation. Carrier suppression and image suppression performance are improved with designated circuit design. The design specially focuses on optimizing the system linearity, enlarging the dynamic range of gain control and enhancing the gain control precision.The integrated transmitter includes PLL, digital interface and the other modules in the uplink. The design is fabricated in 130-nm CMOS process. For high-band (1710MHz—1980MHz) application, the transmitter could achieve -3dBm output power with a -43dBc ACLR using QPSK signal as the stimulation. The corresponding EVM is 2%. Single sideband test results shows the image rejection ratio could be kept below -42dBc while the LO suppression is less than -40dBc in the whole dynamic output range. For low-band (825MHz—915MHz) application, the output power can reach 4dBm and the image suppression and carrier suppression can be kept under-37dBc and-40dBc, respectively for the entire dynamic range. When stimulating with GMSK modulated signal, the system exhibits a phase error of 1.8 degree. The low-band test uses on-chip PLL as the clock in test and the external LO clock can be used for test too.