The. Blackfin561 Interrupt The Mechanisms Of Multi-core Transformation

This dissertation researches the interrupt technology of multi-core embedded system: Firstly, the hardware interrupt mechanism and related supports of the ADI ADSP BF561 dual-core are analyzed. Then the interrupt managements of SMP (symmetric multi-processor) uClinux is studied deeply. Based on the above rusults, the interrupt managements of uClinux have been reconstructed at the BF561 dual-core board.The specific modifications are as follows:1) the interrupt vector table and the interrupt priority of CoreB have been initialized;2) the interrupt handler is transformed, it has increased a determination condition to determine which core responses to the interrupt;3) for the clock interrupt, CoreA and CoreB use the same clock;4) for the inter-processor interrupt,the relevant data structures and processing functions are increased;5) for the exceptions and system calls, CoreB uses the same handler with CoreA. Finally, the mechanism and the implementation of soft interrupt are introduced.In uniprocessor,the interrupt usually is disabled when the core enters the critical section, whereas, in multi-core, spin-lock mechanism is adopted when system accesss to the shared resources; the two-stage mechanism of interrupt is used in BF561 dual-core systems, the capability of parallel processing interrupt at dual-core is fully embodied; the dual-core system makes the communication is possibe between CoreA and CoreB, by inter-processor interrupt, the other core can reschedule a thread, perform a specific function or stop working.Finally, the function test and performance test about interrupt managements on the modified uClinux are conducted. The results show that the interrupt managements of the uClinux at BF561 is capable of supporting dual-core and the interrupt latency is shorter than single-core system. Therefore, it can deal with external events better, and improve the timeliness of embedded system.