Nano-probe In The Lsi Reliability And Failure Analysis Applications

According to the Moore' s Law,the feature size of semiconductor devices continues scaling and the complexity is growing.With the scaling of device size,more chips can be integrated within one wafer.However, with the development of chip manufacturing process,the VLSI chips become more and more complex,and the defects,which will impact the chip performance and reliability,are becoming smaller and smaller to be found. To get the failure analysis capabilities of the deep sub-micron / nano-meter VLSI multi-layer and to achieve the fast＆accurate fault location technology is being strongly demanded.The reliability of integrated circuits is a kind of statistical performance index.It is totally different with quality index and we cannot use instruments,equipment or other means to achieve a satisfactory result on reliability.Through testing and experiment to obtain the necessary data,and then doing data analysis and processing,the statistical reliability index can be obtained.Reliability test is an important method to evaluate the product reliability.In order to ensure the reliability of products at a certain level or to improve product reliability,the reliability accelerated test needs to be adopted to expose the potential defects in the products.For failed samples during reliability test failure analysis needs to be done to find out the root cause of failure.Then effective corrective actions need to be taken to increase product reliability.The nano-probe technology introduced in this thesis is a new developed failure analysis technology.It can be used for fault detection and isolation in the VLSI reliability tests.The most important difference between the Nano-probe technology and the traditional probe lies in probe size.The tip size of the nano-probe is very small,about 50nm,can be used to detect the microstructure of integrated circuits such as metal interconnect lines,a single transistor. With the emergence of nano-probe,the transistor-level failure analysis has become possible,and the failure analysis technique reaches a new level.During the test we selected SRAM chips for study.The SRAM chips were chosen for study because each SRAM memory cell is made up of six standard MOS FET Transistors that are designed with the most stringent design rules. With the structure of bit lines and word lines,the SRAM memory cell can be easy for testing by nano-probe and the following structure analysis. Through the testing and reliability analysis on the SRAM chip,we can use the most stringent standards to evaluate the reliability of the products.The analyzed samples were taken from the failed chips that underwent the test of 48-hour early failure(EFR48h) and 168-hour high temperature operation life(HTOL168h.EFR and HTOL are of accelerated reliability test, in which the ambient temperature is at 125℃and 1.4 times operation voltage is applied.The reliability test is used to detect the chip potential reliability issue.Two samples failed after the reliability test and the failure mode is Single Bit.After sample preparation we performed the nano-probe test to measure the characteristics of six MOSFETs,including the output characteristic curves,the transferring characteristic curves,and the leakage current between source,drain and substrate.Comparing the transistor characteristic parameters of the failed units with that of the passed units and the design specification, such as saturation current(Idsat),threshold voltage(Vt),gate leakage current and so on,we can judge the tested MOSFET is good or bad.For the transistor with characteristic parameters shift,we further do failure analysis,including focused ion beam microscope,transmission electron microscope and X-ray energy disperse spectrometer.Base on the results of nano-probe test and the advanced electron microscopy analysis,we can find the invisible defects in some of the internal transistor.For example, in EFR fail sample we found silicide penetrated into the poly silicon and induced gate oxide break down.In HTOL 168-hour failure sample,the leakage between a pull-down NMOS Drain and the substrate was observed. Through the further TEM structural analysis,in the lattice defects was found in the N-type active region of silicon substrate.From the analysis results of these two samples,we concluded that the defects would induce the reliability test fail.Nano-probe testing and analysis can help us to find the tiny defect in the failed VLSI chip.During the nano-probe testing,we found that the most critical item, which impacts the test accuracy,is the probe contact resistance.The existence of contact resistance affects the accuracy of test results. Nano-probe tip Due to the small size(≈50nm)and the tip surface oxidation layer of the Nano-probe tip,the contact resistance will be very unstable,from dozens to several thousands of ohms range.If the contact resistance value is too large(＞200ohm),it will impact the accuracy of the measurement results.Through a series of improvement measures,including the probes chemical cleaning procedure improvement,the electric method to remove probe surface oxide,as well as the optimization method,we minimize the contact resistance during measurement and the test accuracy of the measurement results become more stable and greatly improved.