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Received By The Radar Signal Digital Reconnaissance Fpga Implementation

Posted on:2009-03-10Degree:MasterType:Thesis
Country:ChinaCandidate:D M JiangFull Text:PDF
GTID:2208360245461226Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
The proliferation of electronic signals in modern combat environments requires the use of sophisticated electronic warfare (EW) receivers. Desirable characteristics of EW receivers include wideband frequency coverage, high sensitivity and dynamic range, high probability of intercept, simultaneous signal detection, frequency resolution and full real-time operation. A classic receiver which accomplishes these requirements is channelized receiver.In this dissertation, some relative techniques of digital channelized receiver are studied, and a proposed digital channelized structure was implementated. The critical issues of the dissertation include as follows.1. A digital channelized approach based on DFT is studied in detail. Compare with the traditional approach, it reduces computational load greatly, and the characteristics of polyphase filters are analyzed and the "rabbit ear effect" is preferably restrained as well.2. According to the features of the IDFT based digital channelizer, a low resource cost structure, whose resource cost hardly changes in spite of the channel number increasing, is proposed,.Moreover, the above structure is separated into four branches synchronously using the method of the decimated in time. Its advantage lies in the hardware resources less than the aboriginal IDFT base digtal channelizer structure and the processing speed higher than the low cost structure. This high efficient structure can be developed for more branches to impelemente in parallel, and then a high processing speed is achieved.3. The processing blocks design and implementation of the high-speed data sampling and digital channelier was introduced using FPGA in detail.4. A low hardware cost implementation on FPGA for radix-4 FFT is studied, which reuse the radix-4 unit and address the memory reasonably5. The performance of ADC circuit is tested. The experimental results of the system indicate that the designed indexes of the digital channelized receiver are satisfying.
Keywords/Search Tags:Digital Channelization, High-speed Sampling, Discrete Fourier Transform, Field Programmable Gate Array, Fold and Unfold
PDF Full Text Request
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