High-performance, Low-power Bus Communication Structure In The Soc Design

On-chip communication is increasingly being regarded as one of the major hurdles for complex system-on-chip (SOC) designs. As technology scales into the nanometer era, chip-level wiring presents numerous challenges, including large signal propagation delays, high-power dissipation, and increased susceptibility. At the system-level, the integration of an increasing number and variety of complex components is resulting in rapid growth in the volume and diversity of on-chip communication traffic, imposing stringent requirements on the underlying on-chip communication resources. The growing importance of on-chip communication adds a new facet to the process of system design. Under the traditional notion of system design, a system's functional requirements are refined and mapped onto a well optimized set of computational resources and storage elements. Today, system designers are required to pay increasing attention to the relatively less understood process of mapping a system's communication requirements onto a well-optimized on-chip communication architecture.In this paper, we introduce network-on-chip(NOC) briefly and analyze the power consumption simply.