Based On The Design Of Sigma-delta Audio Codec

The audio codec is based on sigma-delta modulation and over-sampling signal process. Analog-to-digital&digital-to-analog converter based on sigma-delta modulation and over-sampling filter are the main difficults of the design.ADC sigma-delta modulator implemented by analog circuit could gain high accuracy and be quite insensitive to mismatch and other circuit imperfections; DAC sigma-delta modulator and over-sampling filter implemented by digital curcuit could exploit the enhanced speed, curcuit density and low cost of modern VLSI technologies.This paper will pay attention to designing and implementing digital circuit of audio codec --- DAC sigma-delta modulator and over-sampling filter.In order to achieve higher SNR by the simple architecture, we choose the 1bit single-loop sigma-delta modulator.We could use Chebyshev high filter's function to gain the system parameters, and optimize the locations of zeros and poles for DAC sigma-delta modulator,which both are stable modulators and the input signal of the modulators can achieve maximum.Decimator for ADC and interpolator for DAC make up of oversampling filter.Implement of multi-level filter could save the quantity of calculate and storage for FIR.A novel method of removing DC is used in decimator.Multi-phase architecture of filter is used in interpolator.Because timing is easy to satisfy, how to save areas is taken as the first considered factor.By the methods of multi-level filter, left and right channel sharing combinational logic module and using TDMA in the sequential process of filters, the circuit area could be reduced observably.In order to satisfy most customers'need, the codec support the sample rates from 48k to 8k, there are 9 sample rates; the data-width can be choosed from 16bits to 24bits; there are 4 modes for digital audio interface.After the flow of system design, rtl coding, DFT design, DC systhesis, place and route, STA, and timing verfication, the digital layout is shown in the end. This chip has been implemented in the SMIC 0.18μm CMOS process. Test result shows that the chip has achieved the design target.