Dynamic Can Be Configured To Separate The Study And Design Of The Cache

With the development of microprocessor architecture and manufacturing technology, microprocessor speed increases rapidly, while memory speed lags far behind due to its structure limitation. The overall computer system performance becomes increasingly limited by the latency of memory access. The memory system remains a major performance bottleneck in the modern and future architectures. As an effective method to reduce the performance gap, Cache Unit design and optimization have become an increasingly important factor in determining the overall system performance. When designing the On-chip Cache of an embedded processor, we must employ an effective method, so that we can implement an effective memory hierarchy with low hardware cost.This thesis discusses a dynamic reconfigurable split Cache, based on the Longtium C2 unified Cache. The research work of the thesis mainly includes:1. The Longtium S2 system is introduced and the architecture of Longtium C2 processor is analyzed. The requirements for Cache design are ascertained.2. The architecture, function, and the controlling issue of Longtium C2 Cache are analyzed. The implementation and optimization of the Cache are discussed in detail. The physical floorplan of Longtium C2 Cache is presented.3. Based on the Longtium C2 Cache, the configuration principle, configuration algorithm, configuration parameters and the other related issues of the dynamic reconfigurable split cache are analyzed. Finally, a dynamic reconfigurable split cache is presented.4. The simulation model of the dynamic reconfigurable split cache is built and simulated on the basis of Longtium S2 system. The performance parameters are extracted when it is simulated. Under the Longtium S2 design environment and constraint script, the timing requirement of the design is estimated by the synthesis tool. The experiment result shows the dynamic reconfigurable split cache improved the processor performance.