The Quadrature Decoder / Counter Interface Ic Design And Simulation

With developing of micro-electronics manufacture and techno-design, three are more and more transistors on one chip. The using of EDA tools for integrate circuit(IC) , make the design of chip expend to high integrative and intelligentize continually. The design of Quadrature Decode/Counter Interface ICs also have happened great change in modern digital design.Nowadays, applications of Quadrature Decode/Counter Interface ICs in high-performance motor control systems have been widely developed and the environments require Quadrature Decode/Counter Interface ICs to have higher feature of real time. For completing Quadrature Decoder and Up/Down Counter, it needs special hardware circuit or microprocessor. In the paper, we have completed a kind of Application-specific Integrate Circuit (ASIC) LC7708A1 that used to control the rotate speed and veer of high-performance motor control systems. The Decoder Interface IC that including digital filter block,quadratuer decoder block,up/down counter and bus interface, could improve the capability of system greatly and reduce the using of software for systems. It could be a good way of hardware for controlling of motor systems.For completing practical need best, the design of LC7708A1 which have completed practical need for controlling the rotate speed and veer of motor systems have assimilated the excellence of most kind of domestic and overseas Quadrature Decoder/Counter Interface ICs. The primary innovates as follows:1. We have achieved the design of 32 bit up/down counter.2. The problems of counter output astaticism and data correlation have been resolved by inhabit logic and counter-in block. So the veracity of count system is enhanced.3. In order to get high performance of input quadrate signal, the LC7708A1 has designed the digital filter block and Schmitt which in I/O blocks that enhancing the anti-jamming ability of system.4. Using full 4x decoder, enhanced the decoding ability of system to the input quadratic signal, and enhancing sensitive of counter block.The design process is performed top down using Verilog HDL. The whole LC7708A1 core has been coded for synthesis in Verilog HDL. The test-bench is also coded here. Function has been verified by testing the machine code on the test-bench. Available gate net-list has been gotten by logic synthesis and gate level verification. Using tools of auto place&route, the layout has been primarily finished.