X86 Instruction Launch Decoding Control Unit Design

CISC instruction is complex in function and variable in length. So research on how to design a suitable and effectual instruction decoder can speedup the instruction decoding, enhance the efficiency of the instruction pipeline, and consequently improve the performance of microprocessor effectively.Based on the National Defense Preliminary Research Projects, the author has taken part in the research of 32bit CISC microprocessors "LongtiumC2". "Longtium C2" is compatible with Intel486DX4 in instruction set, design using 0.18μm ASIC library, design working frequency is 133MHz, The author finished the design and verification of the instruction decoder. In addition, this paper analyzes the instruction decode logic for dual issue superscalar microprocessor.The research work of this paper mainly includes:1. Deeply studied the instruction type , instruction format, data type , addressing-form of "LongtengC2" instruction set.2. Designed the instruction decode unit of "LongtiumC2" and analyzed each functional module of the decoder unit..3. Given a model of superscalar dual issue microprocessor, described the pipeline, instruction prefetch mechanism and execution strategy of the model.4. Completed the design of the X86 instruction decoder logic for dual issue superscalar microprocessor.The dissertation work plays a great significance for studying the instruction decoder logic of high performance microprocessors for both single issue and dual issue. The research work offers design consideration and technological reserves for further advanced microprocessor designs.