Research And Implementation Of The Soc Embedded Microprocessor Debugging Technique

Now the embedded processors have been the central part of SoCs (System on a Chip). Since the SoCs have integrated more and more units, and due to the limitation of SoC's footprint and pin numbers, the traditional debugging methods are obsolete and unable to be any help. So making the SoC or the embedded processor support debug function is a necessity.Most of the on-chip debug systems are based on one property: debug mode supporting of CPU. Because an 8-bit processor IP core that does not support debug mode is applied in the PSTN short message terminal SoC, a design of on-chip debugging facilities for this CPU is introduced. It preserves structural integrity of the CPU by managing the its clock externally and implements debug functions such as instruction/data breakpoint, step, run/stop, CPU reset, read CPU kernel registers, read/modify external memory and in-circuit programming with only a small hardware overhead. The debug command configuration and execution are totally independent of the CPU so that the CPU can run in real time.Another debugging method that does not add any additional hardware to the SoC but utilizes the UART (Universal Asynchronous Receiver and Transmitter) of the SoC is also introduced. When the on-chip real time debug system can not be designed for some reason such as time constraint, this purely software implemented debug system is also good enough.Using the above two debugging methods, some key software design techniques in the PSTN short message terminal SoC are studied and a demonstration system including all the programs from data link layer to application layer are completed.The two debugging methods and the whole demonstration system mentioned above have been verified on a platform made of Spartan III xc3s200 FPGA.