High-density Gigabit Ethernet Interface And Realization

Interface is an important part of router, which directly influences the performance of a router. Gigabit Ethernet line-card, as one of the most important line-cards supported by Terabit Router, its design and implementation is an important content for research. In this paper we have had a research about the key technology to design and implement a Gigabit Ethernet line-card with high-density interfaces, and described the implementation scheme of the line-card that supports Multiple Protocol, and then a detailed analysis of the implementation technology for the hardware system is given.The main work of this paper is as follows:1. By establishing the queuing-model for Gigabit Ethernet line-card with high-density interfaces, the requirement for the buffer size and schedule policy are analyzed, the two schedule methods based on packets and chips are compared,2. To guarantee the fairly sharing of the bandwidth between all interfaces, the schedule policy Deficit Weighted Round Robin (DWRR) which is based on packets is adopted in the input link control circuit; To improve the using efficiency of buffers and decrease the ratio of packet lost, the schedule policy Combined Input-Output Threshold Round Robin which is based on chips is adopted in the output link control circuit;3. A new algorithm of Diagonal Interleaved Parity is developed for the data with bit-width configurable, which can be realized in FPGA, so the realization of POS-PHY Level 4 in FPGA is resolved.4. By analyzing the realization of scheduler, a kind of scheduler designed with masker and Priority encoder is given and the efficient of scheduler is increased.5. Based on the need of Gigabit Ethernet line-card with high-density interfaces and the principle of Gigabit Ethernet, this article gives a detailed design scheme of Gigabit Ethernet line-card and divides it into modules logically and realized their functions.6. By the implementation of POS-PHY Level 4 in FPGA, the reliable high-speed transition of multi-channel between a MAC layer device and a logic link control (LLC) layer device is realized.