Mcu8051 Ip Core Design

The thesis discussed about how to implement the single chip machine Intel mcs8051 soft core on the device of Cyclone FPGA designed by Altera Company. The soft core was designed by the VHDL Language. According to the FPGA design flow, the system was synthesized, fitted, assembled, time analyzed and implemented by the integrated tools in Quartus II, also was verified by ModelSim 5.8. This paper mainly introduces the design of msc8051 soft core that satisfied all the functional and timing requirements of standard Intel mcs8051.First, the thesis introduced the internal architecture, design method and coding style of the whole system. Then it detailedly introduces the design of every module and the verification method. After that, the thesis shows the implementing results and the timing simulation oscillograms.While designing the system, we spent a lot of time in considering how to divide and define each module and how to coordinate and interconnect these modules. I followed the top-down method to design. First defined the top module, and then divided the top module to several independent small units. In the internal small unit, I design the control signal and the operation of appointed unit according to function and timing demand. As for the interconnection of modules, I defined the interface signal to communicate between them. When I construct the logic, we pay more attention to make the soft design close to the hardware. So I can effectively make use of hardware resource on FPGA and get a high speed with a low hardware spending to satisfy the demand of the cost and performance. In recent years, using HDL (hardware description language) to design electronics system is a very popular method. Almost in all digital system design we integrate IP core such as microprocessor and rom/ram to FPGA to implement SoC(system on Chip). In built-in system, 8 bits MCU Micro Control Unit) still is the main choice because of the characteristic of application object and environment in low level.