Based On Boundary Scan Test Algorithm And Bist Design Technology Research

With the speedy development of Very Large Scale Integrated circuits (VLSI), 90-nanometer technology has been applied in current IC manufacturing. Numerous chips that contain more than 10 million gates are being produced. Smaller and smaller the chips packages becomes, denselier and denselier the chip pins place, and more and more components the Printed Circuits Boards (PCBS) assemble on. as a result, interconnect testing of chips is in urgent need to resolve. On the other hand, there are a large amount of nodes, which are inaccessible from outsides, within chips or functional blocks. Testing such inaccessible nodes or blocks is a challengeable task. With the faster progress of VLSI technology, testing circuit boards by ICT probes has become more difficult than before, Design-For-Testability (DFT) proposed in recent years is an efficient way to overcome IC test difficulty. DFT technique requires the interposal of test problem at the beginning of electronic system design, so-called Design-For-Testability of system. Boundary Scan Test (BST), as one of DFT techniques that inserts DFT into silicon chips, supports test and Built-In-Self-Test (BIST) at all hierarchy level such as system, board and chip level etc. Digital integrated circuits in common use such as DSP, FPGA, CPLD and high density RAM all have been equipped with BST interfaces, and been standardized, corresponding international standard is IEEE1149.1.But successful application of BST technique reported in literature is much less than their engineering actual demands. Author's researching in this thesis is rightly based on above facts. BST and BIST theory, solution and application based on BST are studied in this thesis also. Work focuses on test algorithm, design, usage and BIST based on BST. Design principle and methodology of DFT in BST are discussed, fault models of interconnect on a circuit board and equivalent exchange are done in order to simplify test process. Mathematical models of BST are established also in this thesis. Based on above principle and methodology, test stimuli generation and test response analysis of boundary scan interconnect test are studied .Two optimal boundary scan interconnect test algorithms are presented. Using DFT methodology of boundary scan, DFT of circuit board is finished, by two optimal algorithms, test effectiveness and correctness is validated.BIST scheme based on boundary scan is presented also, discussion is placed focus on design method of pseudorandom test, relating circuits design and test simulation are finished and implemented also in this thesis. Self-test circuits of multiple boundary scan test structure on board level, system level and a boundary scan framework for an ASIC circuits and its BIST implementation are designated also in this thesis.Theoretical research and experience results proved the correctness of proposed algorithms and design methods in this thesis.