Video Post-processing Chips In The Core Algorithm Implemented In Hardware And Chip Design For Testability

Digital Television (Digital TV), as the third generation Television Technology, has become the most important industry in this century. It is now the focus of the technical contest all over the world. It reflects the general competence of a country's IT technology. In our country, the DTV industry has already started in 2003, and by the time 2015 we will finish the transforming from Analog TV to Digital TV.There are altogether three main chips in the Digital TV's receiver, the channel demodulating chip, the source decoding chip and the Post-process chip. With the appearance of various kinds of new functions and display devices, the Post-process chip has become the most valuable one in Digital TV. It is very important to design and manufact this chip with our own independent intelligence property both for marketing and financial reasons.From Jun.2002 to Nov.2003,1 had been an intern in the National Chip Technology Company. As a core engineer and developer in the Post-process Chip Project, I took part in the whole design process of this chip and accumulated a lot of knowledge, skills and experience in ASIC design and DTV techlonogy.This paper focuses on the core algorithms in the Post-Process Chip and their hardware realizations in ASIC. After that, it introduces the design for test techlonogy in this chip and some valuable and important methods of debugging and testing for both the chip and FPGA systems.The main contributions of this paper are discussing the core algorithms in Post-Process Chip and their implementations in ASIC. It also proposes some constructive ideas of the debugging and testing of the ASIC and FPGA systems.