Digital Multiplexer Fpga Design And Realization

The subject is mainly accomplish a digital multiplexer by FPGA. The function can be accomplished that multiplexes four branches of 2.048Mb/s into one data flow of 8.448Mb/s and then demultiplexes the data flow into four branches, positive justification used during the course of multiplex. The code of the four branches can be the NRZ or HDB3 who is appropriate to be transmitted for a long distance. The clock recovery circuit and clock smooth circuit are accomplished with phase-locked loop (PLL) in this subject. In the article, at first, common problems of line coding are analysed; the second, the elementary theory of positive justification is analysed, and the general method about how to design the digital circuit with FPGA is narrated; At last, the author had analysed the jitter in this subject, such as the jitter generation classification and how to minimize jitter, analysed the waiting jitter introduced by positive justification and phase jitter introduced by the phase-locked loop circuit, simulated and calculated the relationship between the jitter of phase-locked loop and its bandwidth with the Matlab.The following tasks are performed by the author:1. The design and debug of the multiplex system and demultiplex system are accomplished by FPGA.2. The design and debug of line coding HDB3 are accomplished by FPGA.3. The gappy clock is recovered by the PLL.4. Jitter generated in the multiplexer and PLL are analysed and simulated.5. The error bit rate of the multiplexes is tested with the error and jitter test set, and the error bit rate is up to 10"9.