Dsp Implementation Of An Acelp Algorithm

With the development of wireless communication, multimedia communication and secrecy technology, it is increasingly important to reduce the rate of speech coding so as to save frequency bands as many as possible, so brings urgent demand for ? research of speech compression algorithms and their real-time implementation. In this paper , the key issue is how to design a DSP system, which implements the speech- coding solution in TETRA. The kernel of the speech-coding solution in TETRA is a sort of ACELP algorithm, which is a kind of improved CELP algorithm, and obtains the high speech quality at the rate of 4kbps. In chapter 2, its principle is described briefly. This paper introduces software and hardware designing, and some key techniques for the real-time implementation of the ACELP algorithm based on 1MS320VC5402 chip in detail. As a result, one full-duplex implementation needs 34MIPS, 6 K words of program memory, and 6.5 K words of data memory.