Research And Implementation Of Radar Signal Sorting Algorithm Based On

Radar signal separation is a very important signal processing stage in radar reconnaissance system. Implementing the signal separation stage by FPGA will bring crucial improvement to the performance, miniaturization and reliability of a system. Against the missile-borne background and based on Broad First Searching Neighbors (BFSN) clustering and Cumulate Difference (CDIF) histogram algorithms, a research on implementation of radar signals separating completely using the programmable logic resources in a FPGA was carried out. A separating architecture based on a FPGA was proposed in this thesis, and further programmed in verilog hardware description language (HDL). A testing hardware platform on the basis of Xilinx Virtex5FPGA was designed, and experiments of separating simulative radar signals based on it were performed. The results proved the designed architecture’s capability of separating mixed signals coming from unknown regular radars, frequency-jitter radars and frequency-agile (including ultra wide band radars) radars, meanwhile estimating radar parameters accurately. The data processing speed was fast enough to meet the real time separating requirements in dense signal environment.