Fpga Chip Tile Element Modeling And Fault Coverage Analysis

FPGA is a kind of widely used programmable logic devices. FPGA has filled the defects of cost and design cycle of ASIC design. FPGA has three main parts:the logical resource structure, interconnect structure, and programming point configuration.This paper has finished the modeling of the FPGA chip, including the modeling of unit TILE which has the basic logic resources and interconnect resources of the FPGA chip. This paper has designed the function simulation model of unit TILE, the process of the predigestion of the interconnect struct in TILE and the process of the programming point configuration. With these models,this paper has also finished the function simulation and verification of the TILE. In addition, this paper has used TurboFault to finish the fault coverage test of the test patterns designed for the unit SLICE which has the main logic resoutces in TILE.After finishing the test, this paper has designed the process of the fault coverage test. Finally, this paper has concluded and analyzed the fault coverage reports, and found some faults which haven't been covered before.So, this paper designed some new test patterns to cover these faults as much as possible.In order to finish the modeling and simulation of TILE better, this paper has put forward a new method in the modeling of logic resources and predigestion of interconnect resources, and has designed a new method to finish the programming point configuration from a file of configuration information. This article has programmed the scripts which can run this process automatically, and finished the process that generate the function simulation model of TILE and the programming point configuration from the file of configuration information designed with the test patterns.lt helps to finish the fault coverage test of these test patterns, also it provides the basis for the full FPGA chip function simulation.After analyzing the fault coverage reports, this paper concluded the faults that not covered with the TILE model as the simulation and test model, and designed some test patterns for a single SLICE.The fault coverage rate increased to 93.4% finally, and evaluated the effectiveness of these test patterns.