Lithography Feasibility Tests And Its Optimization Method

As VDSM (Very Deep Sub-micron) era has come in IC design, Sub-wavelength Lithography is widely used in semiconductor manufacture process. That makes the printed shapes on silicon wafer are not the same as mask patterns. The distortion in pattern transferring process may influence functionality and performance of IC products and lower the production yield. Resolution Enhancement Technologies are now used in Sub-Wavelength Lithography circumstance to partially solve the incurring manufacturability problem. However, with the Sub-Wavelength Lithography continues extending to its physical limit, new kinds of problems of IC manufacturability and yield keep emerging. This is one of the most concerned research issues for global IC industry and academia now.Synopsys, the leading EDA supplier, developed Prime Yield LCC for Lithography Compliance Check, which is based on Hercules physical verification tool. User can do OPC (Optical Proximity Correction) simulation and LRC (Lithography Rule Check), during chip design stage to predict the manufacture problem and fix them before delivering the chip design to the foundry to reduce the production challenges and improve the yield.However, in the real design process, the extremely slow performance is the key bottleneck of LCC. Being part of the LCC Research and Development team, I carefully studied the whole LCC processes and the existing problems, developed more effective checking rules, proposed several performance improvement methods, and finally reached 5X performance improvement of LCC. This thesis first introduced the basic LCC process, and then delivered the better checking rules, finally emphasized on the 2 performance improvement methods. With the dramatically performance improvement of LCC, it is possible to make LCC be part of the physical implementation flow.