.65 Nm, Process 12-bit 50 Mhz Pipelined Adc Design Study

With rapid developing of integrated circuit process, shrinking feature size and supply voltage, and more and more annoying influence caused by all kinds of nonideal physical effects in advanced technology, design of mixed-signal integrated circuit confronts really a great challenge. As the interface of analog and digital world, development of analog to digital converter (ADC) has been pushed to the direction of advanced process by its wide application scenarios and the needs of SoC integration.The pipelined ADC has become one of the most popular architectures among all kinds of ADCs. In this thesis, an analysis of the principle, structure, and nonideal factors in pipelined ADC systems is explored at first; thereafter, the characteristics of 65-nm CMOS process provided by SMIC, and their influences on mixed-signal integrated circuit design are studied. Based on these, a 12-bit 1.2V 50MHz pipelined ADC is presented.The ADC converter is implemented in hybrid pipelined structure, adopting 2.5 bit per stage for the first two stages,1.5 bit per stage adopting OTA-sharing as the following six stages and a 2-bit flash ADC as the last stage. A front-end sample and hold circuit is maintained to ensure the performance when the frequency of the input signal is higher than the nyquist frequency. A two-stage amplifier is used to achieve the high-gain, high-bandwidth and high-swing with the low power supply. In the amplifier, Miller+Cascode hybrid compensation is used to reduce the power and eliminate the influence of highly process-related zero-adaptive resistor. To further cut the power consumption, the OTA-sharing technique, along with the capacitor scaling down and dynamic comparator are used.This ADC is fabricated in SMIC 65nm,1P7M mixed-signal CMOS process, and the power supply is 1.2V. This chip occupies an area of 2.87×1.55mm2, consuming 57.1mA. In SS comer, the ADC achieved a signal-to-noise-and-distortion ratio (SNDR) of 73.2dB, SFDR of 81.1 dB for an input of 23MHz sinusoid when the sampling clock is 50MHz.