Design And Implementation Of The Sopc-based Multi-channel Pulse Counter

Multi-channel counter is useful in many scientific experiments that are carried out in astronomy, physics, and biomedicine. In most traditional multi-channel counter systems, the control modules are often realized by MCU, DSP or FPGA/CPLD. MCU and DSP are suitable for implementing complex control functions, but it's hard to time accurately because of the uncertainty of software's running. FPGA/CPLD is easy to time accurately, but it's hard to achieve complex control functions. This article comes up a noval method of eliminating the defects of traditional multi-channel counter systems. Utilizing SOPC, it's easy to integrate Nios II processor in FPGA as the control module, which possess all the advantages of MCU and FPGA. The pulse count module is also implemented in FPGA. Because both the pulse count module and the control module are in one chip of FPGA, the system is configurable and expansile with a small size. The multi-channel counter system could communications with computer by RS232. The computer send orders to control the work modules of the multi-channel counter system, which can work in cycle repeat count module or real time display count module. In addition, the system can be also use to measure the temperature and pressure of the environment. The main contents are illustrated as follows:(1) The hardware schematic and the devices used have been generally introduced.(2) The inside modules of FPGA are designed. A 16 channel gray code counter are realized, that can avoid sample error when the system is working in real time display module.A timing module generated in FPGA is adopt to realize precise timing. Using parallel CRC account module can get the CRC of the output of the pulse count module rapidly.(3) The SOPC platform is configured based on practice requirements and then the Nios II processor is generated.(4) Application software is designed. The communication protocol between computer and counter system is designed. The communication reliability is improved by using some methods such as CRC and responsion. A parallel method to deal with count and sending result is realized, which improved the system's efficiency. (5) System debugging and testing is applied to evaluate the overall performance of the system. The system can meet the requirements. The count rate of the system is up to 272MHz.