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Multilevel Converter Pwm Control Method

Posted on:2008-07-30Degree:MasterType:Thesis
Country:ChinaCandidate:X XinFull Text:PDF
GTID:2192360212994138Subject:Power electronics and electric drive
Abstract/Summary:PDF Full Text Request
During the effective approaches for high-voltage and high-power applications, Multilevel converters are studied extensively because of their many advantages, such as their low voltage stress on power switches, low harmonic and EMI output, its corresponding PWM control methods also have become a research hotspot.This paper analyzes the multilevel topologies and operating principles in detail, the advantages and disadvantages of the topologies are presented in summary. The PWM control is the key technology in multilevel converters. The SHEPWM and the CO-SFO-PWM are researched extensively on the foundation of analyzing the different carrier-based PWM methods of multilevel inverter in this paper. The validity of the CO-SFO-PWM method is demonstrated by simulation of five-level inverter. The simulation results indicate that the CO-SFO-PWM strategy exhibits the good harmonic characteristic in low modulation index and has higher DC voltage utilization. The principle of SVPWM method is also analyzed in this paper, the correlation between the carrier-based PWM and SVPWM is established.The paper presents a novel carrier-based PWM method to take advantage of all levels in the inverter even at low modulation indices. The simulation results indicate that the novel PWM strategy increases device utilization and enables the inverter to switch at higher frequencies at modulation indices.Diode-clamped multilevel inverter has been attracting wide interests in high voltage and high power application field because it does not require a separate dc power source. However, one of the major limitations which makes it not widely used in power transfer is the dc bus voltage unbalance. In this paper, an auxiliary chopper circuit which is controlled by hysteresis-band is proposed on the foundation of analyzing the mechanism of dc bus voltage unbalance in diode-clamped multilevel inverter. The simulation results indicate that employing this circuit can maintain the voltage balance, and the output voltage exhibits good harmonic characteristics.A diode-clamped multilevel inverter experiment system which employs the SHEPWM method is built, the system is constructed by the TMS320F2407 DSP and the ACEX EP1K30TC144—3 FPGA, the DSP takes charge of sample and control, the FPGA is in charge of the generation of the PWM , and the waveforms are presented.
Keywords/Search Tags:multilevel converter, diode-clamped, carrier-based PWM, low modulation indices, voltage balance
PDF Full Text Request
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