Automatic Power Analysis Of The Transformation From Floating-point To Fixed-point For Fpga-based Digital Signal Processing Systems

With the success of battery-based wireless communication systems and personal computing devices, low power has become a key issue in Digital Signal Processing (DSP) design. As a result, designers are now encouraged to consider the impact of their decisions not only on speed and area performances, but also on power consumption throughout the entire design process.On the base introduction of the principal technology of FPGA dynamic reconfiguration and methods of low power in IC circuits, the importance and imperious requirement for low power in dynamic FPGA reconfiguration are stated, which methods are different levels form layout ones, logic ones, RTL ones, behavior ones, System ones to abstract ones. After detail discussion and research for various levels, a full set of low power methodology for application of basis of dynamic FPGA resources has been formed and basically an initial theory system has also been formed.This paper concentrates on low power technology of wordlength optimization of DSP system algorithm during the process of fixed-piont transformation. After introducing the EDA tools and transformation flow of floating-point to fixed-point, a fast and flexible accuracy-guranteed fractional wordlengths optimization approach for floating-point to fixed-point transformation is presented.This paper presents an automatic power estimation methodology, which can provide accurate dynamic power consumption distributions of DSP com-ponents implemented on Xilinx FPGAs. Additionally, the de-pendences of power consumption on system level parameters, including clock frequency, area utilization ratio and activity rate, are investigated from sensitivity metric. According to the experi-mental results, several power optimizations can be performed at the early stages of design flow.