A 16 Bits Lower Power Audio Sigma-Delta ADC Design

During recent years, the over-sampling and noise-shaping technology of sigma-delta modulator is widely used in the interface between analog and digital circuits. The two kinds of technology have some advantage in realizing high precision analog to digital converter, simultaneously decreasing the system power. Sigma-Delta ADC requires imprecise matching circuits comparing other kinds of ADC. Sigma-Delta modulator work normal in low supply voltage, so it reduces system power dissipation.This paper mainly researches lower power audio sigma-delta ADC. The input signal frequency 20 kHz is realized, and the output rate of decimation filters is 44.1 or 48 KHz. A third-order single loop sigma delta ADC suitably in lower power design is presented in this paper. This paper also gives some research on first order and second order sigma-delta modulator. The integrator coefficients are optimized by MATLAB simulink tools, and give precise modeling of no ideal factors (such as the output voltage range limitation, the slew rate limitation, operation amplifier bandwidth limitation, nonlinear characteristic of switch, and kT/C noise).These modeling makes the behavioral simulation results accordance with transistor level simulation. The poles of modulator close loop optimized by MATLAB simulink SDtoolbox. In circuits design, cross couple transistors which improve the operational gain are employed in first stage of operation amplifier, and class AB output was adopted in the output stage. Class AB output increase the output range, and decrease the supply voltage. The differential input is employed in sigma-delta modulator. The single to differential circuit is employed and differential output signal THD (Total harmonic distortion) is -94dB, so it does not influence the modulator THD. The first stage of decimation filter is CIC, the second and the third stage is halfband filter. The decimation filter is simulated by spectreverilog simulator, and the testbench generated by sigma-delta modulator realized by verilogA. It reduces the simulation time dramatically.The prototype, fabricated with SMIC0.18-um CMOS technology. The prototype achieves 75dB SNDR in 20-kHz signal bandwidth with oversampling ratio of 128. The sigma-delta modulator consumes 0.9mW, and the digital filter power consumption is 8mW. The core chip area of sigma-delta modulator is 0.33 mm 2, and the digital filter core chip area is 1.5 mm 2...