Research And Design Of A High Resolution Successive Approximation Analog To Digital Converter

Digital signal processing has the multi advantage of strong noise tolerance ability, easy to integrate, low power consumption, low cost, so more and more signal processing uses digital signal instead of analog signal. But most of the signals in the nature are analog such as light, heat, electrical, magnetic. To process these signals in computer, we need to translate these continuous time analog signals into discrete time digital signals. Analog to digital converter (ADC) is the module to realize this function. Successive approximation register analog to digital converter is very popular in the portable instruments, industry controlling and medical instruments because it has the characteristics of medium speed, medium resolution, low power consumption and low cost.This thesis is focus on the research and design of medium speed and high resolution successive approximation register analog to digital converter. After comparing several typical kinds of SAR ADC architecture, the segmented capacitor array architecture is used. The most challenge difficulties in high resolution SAR ADC are the capacitors and resistors mismatch and the inherent offset voltage of comparator. So the offset cancellation technique for comparator and self calibration technique for capacitor mismatch are discussed separately. Based on the Huahong NEC 0.35 ?m technology, a 16bit, 294kSP/s fully differential successive approximation register ADC with 5V power supply is designed. The simulation results show that it has no missing code and DNL is small than 1/2LSB when -10mV to 10mV ramp signal is input. At the 141 kHz sin wave input, it achieves the signal to noise ratio (SNR) 86dB, signal to distortion and noise ratio (SNDR) 83dB and effective number of bits (ENOB) 13.59 bit.