Implementation Of Multi-Core Processors In Hardware Environment

Nowadays, the demand of the computer and communication facility to the chip's operational capability inflates rapidly with the development of integrated circuit technological. As the traditional bus was unable to satisfy the high frequency transmission between the modules under the existing material foundation and the manufacturing level, it has become the inevitable tendency that the low frequency, multi-core chip substitutes for the high frequency, single core chip gradually.This thesis aims to the realization of the whole integrated circuit by using ARM9200 to replace the core and ALTERA FPGA to realize the router and bus, estabilishing a platform for four-core's verification. In this thesis, two structures for the multi-core have been realized and uniformed, which are four-core sharing memory structure and four-core interconnection structure respectively.In this structure, the dynamic management carries on the the memory on software with SDRAM which controls ARM as level-one Cache and the outside SRAM as the level-two Cache. By using the multi-stage buffers, the memory utilization ratio has been enhanced obviously compares to the traditional way. In this paper, Network on Chip (NoC) has been used to replace traditional bus construction for the direct communication between the cores. Besides, the node match algorithm was adopted in NoC, and the iSLIP match algorithm under the interconnection structure was substituted for X-Y route algorithm under the traditional Mesh or Tours structure. As the high demand for speed and resources of the NoC, it is essential to determine its buffer size and data delay. This thesis based on the theory of the queue up model, made the comparation of buffer size between 16-core under Tours structures and the interconnection structure by simulating with Matlab and OPNET. The result was that the interconnection structure may cost more area, but reduced the averaged data delay greately and promoted the data transmission speed. In the thesis, the compression of JPEG image was used to verify the performance of four-core platform and the results indicated that it takes 0.179s to processe a 256×256 colored picture under the single-core, and 0.065s under four-core, and the ratio is 2.753.