Optimization And Characterization Of 4H-SiC MESFET With Spacer Layer And Field Plate

Silicon carbide (SiC) is a very promising candidate for high temperature, high power, high frequency, and radiation hardness applications because of its superior properties such as wide band gap, high critical breakdown field, high thermal conductivity and high saturation electron drift velocity. However, as the inherent properties of SiC materials, a high intrinsic surface states and interface states makes SiC microwave power MESFET devices are always faced with uncertainty, such as current instability, current collapse and other performance and reliability issues, especially when the device operates at high frequencies, due to the high density of interface states required for a large charge and discharge time, making channel current switching speed can not keep up the changes in the gate input signal, resulting in the device output power and gain decrease. This is SiC MESFET gate delay (gate lag) phenomenon. For these problems, seeking a solution from the device structure is the only way at present.In this paper, first, the characteristics and future trends of SiC materials and the study of SiC MESFET at home and aboard have been stated. Then the operation principle of the MESFET device is stated. Based on the material parameters of SiC, a two-dimensional numerical model for 4H-SiC MESFET is established by using MEDICI. With this model, the DC performances of traditional 4H-SiC MESFET in both room temperature and high temperature have been simulated. In order to diminish or even eliminate the effect of surface trap and increase the power performance, a spcer layer and a gate field plate has been added into 4H-SiC MESFET device structure. The effects of channel parameters on the device has been simulated and analyzed. The device threshold voltage, leakage current and breakdown voltage will increase with the increase of channel thickness, but the excessive thickness of the channel will lead to short-channel effect. The device threshold voltage and leakage current will increase with the increase of channel concentration, but breakdown voltage will decrease. According to the RESURF technology, the channel concentration is 1.5?1017cm-3, when the largest breakdown voltage is achieved. Then, the effects of gate on device characteristics has been simulated. It mainly includes the simulation of the depth of the buried gate, the gate horizontal position, the gate shape, the gate field plate structure, and the gate length on device characteristics. The device effective channel thickness is reduced with the increase of the depth of buried gate, resulting in the reducing of leakage current and threshold voltage. The horizontal position of Gate will change the gate-drain distance, but will not change the device threshold voltage. When the gate shape is trapezoidal and inverted trapezoid, the threshold voltage is almost unchanged, while changes in other characteristics of the device is small. The gate field plate structure can effectively increase the breakdown voltage, when the gate field plate length is 0.6μm when it get the maximum breakdown voltage, but it will reduce the device leakage current. An increase in gate length will increase the device breakdown voltage, but will lead to a decline in leakage current.