The High-Performance ALU Design Of Multi-Core Microprocessor

Arithmetic logic unit is one of the most important and common computing components in the microprocessor. The speed and power dissipation has a significant impact on microprocessor's performance. The structure of ALU and adder principle is studied in this thesis. According to the characteristics of microprocessor in the network processors, a 32-bit ALU component applied in the micro-engine is designed. It supports all the logical operations and arithmetic instructions of 32-bit micro-engine. By full-custom design, the design optimization is carried out to improve the performance of ALU in the algorithm, circuit and layout level.Through the analysis on the existing ALU structure and the adder principle, the general parallel prefix adder is improved by allelic grouping method to generate carryout. That is parallel prefix carry in group and serial carry between groups.In order to reduce the transistor number of the circuit, ALU is implemented with pass-transistor logic. Through theoretical calculation and Spice simulation, the transistor size of critical path is optimized. When the frequency is 500MHz, power supply voltage is 2.5V, Hspice simulation results indicate that critical path delay is 0.84ns, average power consumption is 40mw, and transistor number is 5008.Under the condition of typical 0.25μm process, the physical examination and parasitic extraction of ALU is completed with Calibre. Hspice simulation shows that the critical path delay of 1.1ns, average power consumption is 48mw; layout area is 0.054mm2.