Research On Microarchitecture Of Media Digital Signal Processor MediaDSP6410

RISC/DSP is a highly cost effective programmable solution to embedded media processing. The author takes part in the research on the media digital signal processor MediaDSP6410(MD6410) based on RISC/DSP architecture. The research was launched by MediaProcessor Lab of Department of Information Science and Electronic Engineering of Zhejiang University. As part of the research results, this thesis focuses on the research and design of 2-issue out-of-order superscalar and dual-threaded microarchitecture.Benchmarking guides the design of processor. The specification of processor design is based on the need of application. Parallelism can be developed in three ways. 8-way SIMD extension maximizes the data-level parallelism of the kernels of video compression algorithms. The compound media processing instructions exploit the instruction-level parallelism and are of good code density. Scalar program sections and vectorized sections can be seen as threads, thus thread-level parallelism can be also exploited.Embedded processor design is constrained by area, power budget and design complexity. A superscalar design of minimized complexity is proposed to improve the performance of executing scalar code. A register renaming mechanism which combines the rename map table and issue buffer without operands is proposed. To simplify the design without much sacrificing the performance, media register and store operand are not renamed, so the compound media instructions and RISC instructions are serially executed. The data hazard detection logic is reconsidered to avoid the critical path caused by global stall. Experiments show that MD6410 can work at 300MHz with TSMC 130nm technology in worst case. The performance of execution scalar code is 1.6 to 2 times of the original design at the area cost of 3.3%.Multithreaded extension is aiming at developing parallel algorithms and improving processor resource utilization and throughput. To maximize hardware resource utilization, a map relationship between parallel algorithm and multicore and multithreaded architecture is suggested. The tradeoff of microarchitecture design is carefully examined. The instruction decoder is designed to facilitate prioritized thread scheduling. The instruction issue logic considers the utilization of the shared execution pipeline. And the interface between direct memory access and scratch-pad memory is refined. A non-blocking message passing mechanism is proposed to implement thread synchronization, which makes flexible switch between multithread and superscalar modes possible. Experiments show that the throughput is 26%～35% improved at the area cost of 5.9%.