Design Network Access Controller For NoC-Based MPSoC

As the rapid development of semiconductor and IC technology, more and more transistors can be integrated on a single silicon chip. Multi-core SoC (System-on-Chip) design based on chip bus began to encounter new problems and challenges. The issues such as poor scalability,low parallel communication efficiency,difficult clock synchronization are being becoming a bottleneck restricting the development of SoC. NoC (Network-on-Chip, NoC) technology, with its high throughput, reliability and scalability characteristics provides an effective interconnect solution for large-scale CMP (Multi-Processor on Chip), and gradually becomes a focus research area of integrated circuits.Based on the above background, this thesis proposed and implemented an efficient Network Access Controller (NAC) unit to provide a key component for NoC. The NAC has sending and receiving duplex mode, supports cross-clock domain data exchange, contains a series of configurable registers, and introduces a Message Table (MT) based receiving method which makes data transfers more efficient by recording and updating receiving configuration information of messages automatically.In the thesis, we first proposed a hierarchical OSI reference model for NoC, with different levels of task partitioning and data definitions. Then made function definition and module division for NAC, and mainly described the detailed design process of each sub module. Finally built a simulation platform to conduct the design verification and performance analysis. The result shows that the NAC can meet the design requirements well in respect of function, size, frequency, communication efficiency, etc.