Research Of Key Techniques On A Parallel And Reconfigurable ECC Coprocessor

The elliptic curve cryptography (ECC) can be used in broad domains and has many international and commercial standards. The types and parameters of elliptic curves can be selected in a wide range. There are many scheduling algorithms of group arithmetical layer and curve arithmetical layer. The implementation methods on finite fields are also very abundant. Though the benefits of application and implementation that ECC gains, it also challenges the compatibility and flexibility of hardware chip of ECC. On the other hand, in high-end domains, such as network sever and CA, the ECC accelerator is required to provide high throughput because the secure connections are so many in high-end servers. Therefore, improving the flexibility of the single ECC chip, which can support parametric curves and multi-fields, and synchronously boosting the ECC processing have now become a hotspot and difficulty of implementation technology of ECC.The key techniques of an ECC application specific instruction coprocessor for high-end application are investigated in order to boost the flexibility and speed of the ECC chip. Four aspects of work have been done in this paper, which are enumerated as follows:1. Under the standard projective coordinates, the modified parallel scheduling algorithms of ECC point addition and doubling over GF(p) and GF(2~m) are proposed. The parallelism of modular multiplication, modular addition and modular subtraction is improved by introducing an additional modular multiplier and necessary temporary variables. The analysis indicates that the time of ECADD and ECDBL parallel scheduling algorithms decreases over 50% than that of serial algorithms in the way of bartering area for time.2. The scalable dual-field Montgomrey modular multiplier is modified by introducing a noval triple-clock modular multiplication processing element (PE). The delay of critical path of the multiplier is decreased by replacing conventional dual-clock PE with our novel triple-clock PE. In the micro-architecture of triple-clock PE, a hybrid dual-field Wallace tree is modified to compress the partial product. A high speed hybrid adder is designed to translate the interim redundant numbers to normal types, which reduces registers of retiming. The synthesis shows that the multiplier can maximally work at 240 MHz under the SMIC 0.18μm CMOS technology by the modified measures above. It is only 0.23μs @240MHz to compute a 256bit modular multiplication over GF(p).3. A reconfigurable modular addition/subtraction module is designed, which achieves scalability by intruducing multi-precision modular addition and subtraction algorithms. By adopting the concept of reconfigurability, modular addition and subtraction over GF(p) and modular addition over GF(2~m) are designed in a unified module. This method also decreases the chip area of this module.4. With the hardware/software co-design methodology, a parallel and reconfigurable implementation scheme of ECC coprocessor is proposed. The cryptographic protocols and the point multiplication of ECC are computed by software programs, which are composed of main processer instructions and extended application specific ECC processing instructions. The ECC point addition and doubling are operated in ECC hardware coprocessor. The proposed parallel ECC point addition and doubling scheduling algorithms are mapped on a parallel architecture that is based on VLIW processor techniques. The trait of this architecture is that the development of parallelism of VLIW instructions needs not to customize special complier but is ensured by the parallel scheduling algorithms. The analysis indicates that the point multiplication can boost over 100% than the conventional coprocessor by the parallel processing.By our proposed parallel scheduling algorithms, reconfigurable function modules, programmable extended instructions and parallel processing architecture above, the flexibility and processing speed of ECC chip are both boosted much.