Development Of Serial Bus Analyzer Based On Nios

This thesis gives emphasis on the design of serial bus analyzer based on Nios. By detecting the states of the serial bus on the equipment effectively and analyzing them intensively, the serial bus analyzer can provide intuitionistic result for the user, lay out the waves and timing of the bus on the equipment. All of this will make it easy for the developers and conner to analyze questions and locate faults, and also provide effective criterion to identify whether the communication status is normal for the serial bus on the equipment. It will contribute a lot to developing equipments base on serial bus technologies and prompting the modernization of national defense to design high-performance serial bus analyzer.On the basis of sufficient analysis and comparing the foreign products, this design adopted Nios II embedded processor as the central component and the whole scheme is discussed in this thesis according to the project application needs.The hardware of the apparatus is divided into wave sampling circuit, wave decoding module, HDLC protocol decoding module and DA control module. The apparatus is modular designed, which brings convenience to its debugging, upgrade and maintenance. The design of each function unit is introduced detailed including design process and some key diagrams. The key techniques applied in the hardware design are emphasized, including Nios II embedded processor technique, serial bus wave sampling technique, FPGA technique, etc.The software of the apparatus takes the Nios II IDE as the design environment, and the Nios II embedded processor as the running platform. Also, the LCD displaying software and the keyboard controlling software is developed in the software development platform of uVision2.The actual test and experimental results show that the theoretical analysis of this design is correct, the design is reasonable and every of the technical qualification is satisfied with the requirements of the design.