Design And Implementation Of MIPS RISC Microprocessor Control Module

With the development of IC design and process technology, embedded system has been widely applied in many kinds of electronic equipments such as Set-Top Box, mobile communication,smart card etc, beacause of the advantage of high performance,lower power cost and portable.As the core of embedded system,the microprocessor's performance directly determines the performance of system.Especially as a strategy,RISC(Reduced Instruction Set Computer) is becoming more popular in the design of embedded microprocessor.The first step of microprocessor design is determining the instruction set.After comparing some popular RISC instruction set, we choose the MIPS instruction set, and decide to implement 34 instructions of MIPS instrction set. The RISC microprocessor has fixed-length of 32-hit instructions based on three different format R-format, I-format and J-format, and 32-bit general-purpose registers with memory word of 32-bit. In the design of single cycle microprocessor, we use combination logic to realize the control unit.In the design of mutile cycle microprocessor,we use FSM(Finite State Machine) to design the control unit.When the microprocessor is designed by 5-stage pipline, including instruction fetch,instruction decode,execution,memory access and write back.The new problems such as data hazard and branch hazard arise.We design the data forwarding unit and hazard detection unit to solve data hazard.But control hazard is as a result of the branch or jump instruction,so we add comparer and forwarding unit in the ID stage to reduce the delay of branches.All the modules in the design are coded in HDL(Hardware Description Language), as it is very useful tool with its concept of concurrency to cope with the parallelism of digital hardware.To realize the design beased on FPGA, we use HDL to describe the design and simulate every control modual,at last synthesize the microprocessor and implement it on the Spartan-3AN development board from Xilinx.