VLSI Design And Softcore Realization On Bit-plane Coding In JPEG2000

JPEG2000 is a new image/video codec standard, in which there are two new arithmetics, Discrete Wavelet Transformation (DWT) and Embedded Block Coding with Optimal Truncation (EBCOT). Because of being adopted in such two arithmetics, the JPEG2000 become more popular and more flexible in image/video codec field. Meanwhile, the arithmetic also bring in some challenges such as complexion, difficulties of hardware implementation and so on. Such challenges make JPEG2000 difficult to implement more or less, especially with the EBCOT brought in, the speed of whole system become slower. So, how to optimize the EBCOT efficiently is one of the most important problems in implementation of JPEG2000.Since the JPEG2000 standard was proposed, Many software companies have developd their image processing softwares or plug-ins based on the JPEG2000。These are all the promotion of the JPEG2000 standard in commercial circulation。But so far the realization of JPEG2000 hardware is not very mature , Research on high-performance hardware implementation of JPEG2000 is still a research hotspot. Therefore, from the perspective of the practical application, this paper discusses the hardware implementation for the most complex module bit-plane coding in JPEG2000 coding system. I proposed a new VLSI design method for the hardware implementation, and the soft IP core is developed written in Verilog HDL.In this paper, I analyze the basic frame and principle of JPEG2000 first, and then discuss the hardware implementation method focus on the bit-plane coding block which is the most complex part of EBCOT. The three-channel scanning and the number of bit-planes increase the cycle of encoding operation, which consume a large number of clock cycles. While using hardware to achieve this module, the coefficient-bit coding can be dealed directly in hardware and the number of reading operations can be reduced,so the processing performance of the bit-plane coding module can be impoved. After detail analysis of the basic principle of bit-plane and the comparison among current implementation methods, This Paper proposed a new VLSI design method for the hardware implementation. Coefficient bit parallel coding schemes are choosed as a basis for further study. And the detail explaination attached in the following passages of this paper.In my design, the soft IP core is developed written in Verilog HDL. The validity and the realizability of this design are strongly supported by the functional simulation and the verification of FPGA.