Design Of 622MHz CPPLL Based On 0.18μm CMOS Technology

Phase locked loop (PLL) is a circuit that can let the output signal be synchronous with the reference signal in frequency or phase.It has been developed from linear analog PLL with poor performance to modern digital and analog-digital hybrid PLL with high performance and has been widely used in electronics,communication and instruments.Charge pump PLL (CPPLL) has the advantages,such as small locked phase difference and wide capture range,so it has been the main PLL product among numerous PLL technologies.A CPPLL that can be used to the SDH system of fiber communication has been implemented by using the 0.18μm CMOS technology.The center frequency of the input and output signals of the proposed PLL are 155MHz and 622MHz respectively. The proposed PLL can be used in the two velocity levels of STM-1 and STM-4 of the SDH system.A CPPLL consists Frequency/Phase detector (PFD), charge pump (CP), low-pass filter (LF), voltage controlled oscillator (VCO), and frequency divider. CP is the key unit of the CPPLL, it decides the CPPLL's performance to a large extent. There is mismatch between charge and discharge current in CP, aiming at solving the mismatch problem, a novel gain-boosting structure is designed. The proposed structure can greatly improve the CP's output resistance and reduce the channel length modulation effect, so it can increase the match performance obviously. The effect of noise can be reduced through adopting the differential ring structure, linear range can be enlarged by adopting symmetric load, and switching rate can be boosted by adopting positive feedback. Other modules are optimized.All the functional modules of the CPPLL and the system are simulated by using the HSPICE software with the 0.18μm CMOS technology.The simulation results show that the lock time is 4μs and the CPPLL outputs steady 622MHz clock signal, which meet the anticipated effect.