Design And Implementation Of Debug/Test Module Based On JTAG For X-DSP

X-DSP processor,a high-performance 32-bit fixed-point DSP chip,which is independently researched and developed by the Computer College of the National University of Defense Technology. In order to meet the application demands of on-chip debug during the application development stage,as well as the test requirements for the board-level interconnection, this dissertation conducts an in-depth study on X-DSP architecture, a number of SOC On-chip Debug technologys and several Design-For-Test methods.On this basis,a design scheme is proposed which is based on JTAG standard for the On-chip debug and test structure of the X-DSP,and achieved the hardware design,simulation and the design of the debugging driver for IDE.Boundary-scan structure for X-DSP is first designed and implemented in this paper.From the standpoint of improving the stability and flexibility of the design, theory-Based analysis of the Boundary-scan,this topic designed the Boundary-scan control logic and adopted self-designed Boundary-Scan cells to achieve the construction of the Boundary-scan chain.In addition,in order to accomplish the deep intergration of On-chip debug logic and test logic,this article has adopted many solutions,such as expanding the JTAG instruction sets,adding some extra control-scan chains and so on.Secondly,this paper proposes the scheme of X-DSP On-chip debug system based on the above design,has finished the RTL-code design and the verification.By merging the boundary-scan structure and the debug logic,this thesis accomplished the design of the On-chip debug system.Through the control of the pipeline, implemented the basic debugging characteristics,such as external simulation stops, single step,breakpoint operation,etc;Through the JTAG interface to access the On-chip storage space, implemented the storage access control mechanism based on the principle of handshake.Boundary-scan structure supplies the debug logic with control channels and data channels,this avoids the increase in the number of the chip pins and greatly enhances the utilization of hardware resource.After the completion of the hardware design,in order to achieve the synergetic control between hardware and software during debugging process,the debugging driver is accomplished with Win32 API under Visual C++ 6.0 IDE.The System-level verification had benn conducted on the design..The result of the simulation shows that the present system has reasonable structures,complete functions and stable performance,and provides a powerful support for the development of application program and the test of board-level interconnection.