IP Core Design Of High Performance FPGA Configurable Memory

The configurable RAM block is a very important component of FPGA. To meet the users' different application demands,the RAM block must provide good configurable ability. A 4-Kb configurable dual port SRAM with high speed has been designed in this paper. Each RAM block supports multiple configurations. It can be configured to five memory organizations: 4K×1,2K×2,1K×4,512×8 and 256×16. Using various configuration options,the RAM block can create single port SRAM,dual port SRAM,ROM,FIFO,large look-up tables or shifter registers. This paper introduces the complete design method of this configurable SRAM,focuses on the structure design,the functional module design to achieve and circuit architecture to complete various configurable functions. To incorporate the latest developments in the configurable RAM block, it has a certain amount of research on the configurable FIFO control logic that embedded in the RAM block. The chip access time is 5.5ns.The chip can operate normally when the frequency is higher than 100MHz.The simulation and experimental results show that the 4-Kb configurable dual port SRAM achieves a high performance target.