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Research And Design Of 2M Bit Error Testor

Posted on:2010-03-30Degree:MasterType:Thesis
Country:ChinaCandidate:J LiuFull Text:PDF
GTID:2178360275497102Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
2M transmission lines are the basics of PSTN in China. In our country, both Plesiochronous Digital Hierarchy and Synchronous Digital Hierarchy are based on 2M transmission lines. So the performance of 2M-transmission lines directly effect on the transmission quality of PSTN. Evaluating its transmission performance is very significant in the maintenance of the network.A bit error testor measures the transfer quality of the system by detecting its error-code damnification level. A bit error testor is used in the telecom/datacom communication networks' testing and maintenance. It is a basic measure equipment in the telecommunication department. Also, it is necessary communication measure equipment in the acceptance and test of engineering, teaching and relative research. So, 2M bit error testor still has a very big market demand. Under this background, this context advances the research subjuct of research and design of 2M bit error testor. The main content of this thesis can be descripted as follows:Thesis explains the importance and significance of the research subjuct of research and design of 2M bit error testor by analysing the research condition and applied circumstance of domestic and foreign error code testor, and it also advances the main research content of this topic. It adopts DS26521 as the bit error detection core of the bit error testor after studying various design methods of 2M bit error testor, comparing and analysing the merit and shortcoming of these methods. Then it studies on key techniques such as the error code generating in the digital communication system, the analysis of binary pseudorandom sequence, the technique of line encoding and decoding, G.821 protocal, etc. These works swept the obstacle of design. Then it carries on the market investigation and does requirement analysis on the 2M bit error testor, based on this, finishes the total project design. Adopts the solution of DS26521 with 2M signal processing and Single-Chip Microcomputer cooperating control and provides a friendly man-machine interface, in this thesis, module design thinking method is carried on the design of system hardware. The thesis uses C language to design the error detecting core of 2M bit error testor. And it adopts the design of Top-Down ande module design thingking method to complete the system software design . The thesis also researches on the methods of the system's data communication, this system uses I~2C and SPI as the methods of the data communication between the function modules. At last, the thesis gives a test of equipments, and the results show that the indexes meet the requirements, so it can put into use.
Keywords/Search Tags:2M Error code testor, BER, Single-Chip Microcomputer, I~2C, SPI
PDF Full Text Request
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