The Design Of Divider For Frequency Synthesizer Applied In GPS Receiver

The operating frequency of RF Frequency Synthesizer has expanded to Multi-GHz with the global explosive increment in wireless communication market. As a key building-block in RF front-end circuit, Frequency Synthesizer should also fulfill channel switching requirement in communication system.As the block fixing the output frequency of synthesizer, the divider operates at the highest frequency. The performance of it has good influence on the overall performance of synthesizer. For an oscillator applied in GPS receiver, the oscillating frequency is about 3.2GHz, while the input frequency is about 1MHz, so a divide ratio of 3200 is needed. Usually multi-dividers are employed to implement such a huge divide ratio: a multi-modulus prescaler working at high frequency and programmable-divider working at low frequencies. Then the prescaler defines the whole performance of the divider because it runs at highest frequency and consumes the most power dissipation.Phase switching is proved to be the eligible topology for the dual-modulus prescaler. Diverse-switching can ensure the convergence in time domain and avoid the spurs. So the design bottleneck will be the robust MUX block design. Besides, the multi-dividers used in phase-switching prescaler are implemented based on current mode technique, so the static power consumption and the operating frequency will also be important considerations.High-speed digital circuits have more applications besides the prescaler. For a typical GPS receiver, LO buffer is also in the domain of digital circuits. And for LO buffer, important performance will focus on the good driving capability, low power consumption and good noise performance. All of these set good requirements for the circuits design.In this thesis, research on the high-speed digital circuit applications on dual-modulus prescaler is provided. The performance of different topologies is compared. The main work is on a divide-by-31/32 prescaler working at 3.2GHz for PLL and LO buffer applied in GPS receiver. The power supply for it is 2.0V, and its operating frequency can be as high as 4.5GHz, drawing a current no more than 3.5mA under 50oC. The LO buffer includes a divide-by-2 block and the buffer block. When under 50oC and at 3.2GHz, the LO buffer draws a current no more than 6mA, while keeping the output swing of the signal to 800mV (peak to peak). All the blocks have individual LDO Regulator, and layout and post-layout simulation are completed.