High Frequency And Low Jitter Charge-Pump PLL Design

PLL is greatly popular in modern communication and processor field, especially in recent decade, with the fast development in these fields, operation frequency has rised up to several GHz (even tens of GHz). In time domain, the period of clock is shorter and requirement is harder to the jitter. Correspondingly, in frequency domain, it's more rigorous to phase noise. When PLL integrated in one chip with thousands of digital, analog and RF circuits , it's vulnerable to various disturb from other circuits especially digital parts, by way of power supply, substrate, even PCB board. Thus, it's generally sticking point to design a PLL with low noise in SOC. Herein charge-pump PLL is easier to be integrated, lower loss, less jitter, and wider capture range, research of CPPLL is the core of this paper, to realize a 800MHz internal clock for CMOS image sensor.Firstly, the fundamental of PLL is introduced, CPPLL is investigated for its wide popularity as well. On the basis of small signal model of PLL, the characteristics and parameters of the core module is discussed and their influence to the operating frequency and noise performance are comprehensively analysed, such as advantage and disadvantage of different constructures of phase and frequency detector, charge pump, building structure of VCO delay cell and types of D flip-flop in divider. Then, A practical CPPLL, based on SMIC 0.18μm 1.8V standard CMOS process model, is designed as clock-multiplier circuit in CMOS image sensor. Simulation result shows that it works stably with 800MHz output, settling time less than 10μs, loss less than 18mW, noise less than 100mV, and functions correct in expectation.Furthermore, in system desigh level, the loop bandwidth is optimized by programmable current value in charge pump circuit and divider coefficient. In circuit design level, zone-less PFD structure is adopted to shorten lock time, cascode charge pump structure is adopted to avoid the current mismatch by minimizing the overshoot aroused by charge-sharing, consequently presicion reflecting phase error is improved effectively.Differential symmetric structure VCO delay cell has also quite good anti-noise characteristics.